High Speed Board Design Guidelines

When Do High Speed PCB Design Rules Become Important?

A good way to check whether you need to concern yourself with high speed board design guidelines is to layout your new device on a breadboard or a development board. If you can layout your new device on a breadboard, and it works perfectly, then you can probably layout your board in any way you like and the finished PCB will still work. However, high speed devices generally won’t work on a breadboard. This is one reason component manufacturers release development boards for their components, particularly FPGAs, MCUs, RF components, and many other components.

If you can layout your peripherals on top of a development board, and the device works properly, then you can likely layout your new board however you like as long as you follow the stackup design in your development board. In this case, you should also pay attention to the signaling standards (SPI, UART, I2C, etc.) used in the board to ensure signals are not heavily degraded during routing. In many cases, you won’t be able to take such a simple approach, and everything will need to be integrated into a single PCB. In this case, you’ll need to pay attention to the following design points to ensure your high speed signals are not heavily distorted during routing.

What is a High Speed PCB?

When newer designers think about the term “high speed,” they are likely to default to clock rate. However, a high speed design has nothing to do with clock rates and has everything to do with edge rate, or the rate at which the signal level swings between digital states. There is no clear delineation between high speed and low speed PCBs, and new designs with advanced components should be designed with high speed board design guidelines in mind.

In a high speed PCB, the rise time is fast enough that the bandwidth for the digital signal can extend into the high MHz or GHz frequencies. When this happens, there are certain signaling problems that will be noticed if a board is not designed using high speed PCB design rules. In particular, one might notice:

• • Unacceptably large transient ringing. This generally occurs when traces are not wide enough, although you need to be careful when making your traces wider. If transient ringing is quite large, you’ll have large overshoot or undershoot in your signal transitions.

• • Strong crosstalk. As the signal speed increases (i.e., as the rise time decreases), capacitive crosstalk can become quite large as the induced current experiences capacitive impedance.

• • Reflections off of driver and receiver components. Your signals can reflect off of other components whenever there is an impedance mismatch. Whether or not the impedance mismatch becomes important requires looking at the input impedance, load impedance, and transmission line characteristic impedance for an interconnect. You can read more about this in the following section.

• • Power integrity problems (transient PDN ripple, ground bounce, etc.). This is another set of unavoidable problems in any design. However, transient PDN ripple and any resulting EMI can be reduced significantly through proper stackup design and decoupling measures. You can read more about high speed PCB stackup design later in this guide.

• Strong conducted and radiated EMI. The study of solving EMI problems is extensive, both at the IC level and the high speed PCB design level. EMI is essentially a reciprocal process; if you design your board to have strong EMI immunity, then it will emit less EMI. Again, most of this boils down to designing the right PCB stackup.

With these problems in mind, let’s take a look at the important high speed board design guidelines designers should use to combat these signal integrity and power integrity problems.

Impedance Control in PCB Design

The term “high speed” refers specifically to the amount of time a digital signal takes to switch between OFF and ON states. Again, there is no specific rise time that dictates whether a board is in the low speed or high speed design regime. Generally, if the rise time of the signal is less than 5 ns, then you probably need to worry about high speed PCB design rules. However, we can get more granualar than this by looking at the signal velocity, the amount of time required for a signal to travel down an interconnect, and how this travel time compares to the rise time.

PCB Stackup Design

Your PCB stackup is a major determinant of signal integrity and power integrity. High speed signals require a nearby reference plane (power or ground) on an adjacent layer in order to ensure the loop inductance for that signal is low. I prefer to use a ground plane directly below the signal layer, followed by a power plane, but you can certainly use the power plane as the reference for a high speed signal as long as there is a ground plane on the next layer. This is true for digital and analog PCBs.

PCB Return Path Design

This is intimately related to stackup design, although it is one PCB guideline for high speed design that many designers ignore. In a real board, the return path taken by current in your board does not follow exactly below the trace carrying the injected signal. At high speed, the return current is more likely to be confined below the signal trace, but this is not the case at lower speeds. Take a look at this article for more information about PCB return path design.

Without repeating everything in the aforementioned article, I will list some important guidelines that will help prevent undue interference between signals, susceptibility to EMI, and power integrity problems:

• • Don’t route over a ground plane gap. When designing your stackup, you may end up placing a gap in the ground plane to accommodate vias, mechanical holes, etc. Don’t ever route a high speed signal over this gap. By doing so, you increase the loop inductance for that signal. This then increases transient ringing, susceptibility and strength of crosstalk, and changes the impedance of the trace.

• Don’t route digital signals over an analog board section. Digital signals are relatively stable against interference from low-level analog signals as digital components are running at saturation. The same is not true for analog signals. In a mixed-signal board, a digital signal and its return current can induce strong crosstalk in an analog signal, which will greatly interfere with analog components. If you plan your board sections correctly, you shouldn’t have to worry about this.

High Speed Routing Guidelines

In addition to the impedance controlled design points mentioned above, traces should be carefully routed. Here are some of the important guidelines that will apply in any high speed PCB layout:

• • Minimize use of vias. If vias are not properly designed, they can create an impedance discontinuity that causes reflections and attenuation. Ideally, the number of vias on an interconnect should be limited to no more than 2 in total.

• • Use length equalization where necessary. For differential pairs, each end in a pair needs to have the same length within some specific tolerance. This is very important for ensuring that the receiver can cancel out common-mode noise on the interconnect. For single-ended signals, multiple signals may need to be routed in parallel (e.g., on a bus) such that the signals arrive at the destination at the same time.

• • Prefer shorter trace lengths. Signals lose energy over time to dielectric absorption. This means you should opt to use shorter traces in order to minimize attenuation. Many signaling standards (e.g., LVDS and USB) will specify a maximum allowed PCB trace length.

• Pay attention to trace spacing. Signals should not be placed too close together in order to reduce the strength of crosstalk. Note that you can never eliminate crosstalk, but you can reduce it by placing the right amount of space between neighboring signals. Don’t trust the old “3W” rule here. Instead, run a crosstalk simulation in a simple layout to determine the right trace spacing.